View BCM20730_8992409.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? cyw20730 single-chip bluetooth transceiver for wireless input devices cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-14824 rev. *j revised april 25, 2017 the cypress cyw20730 is a bluetooth 3.0-co mpliant, stand-alone baseband processor with an integrated 2.4 ghz transceiver. it is ideal for wireless input device applications including game controllers, keyboards, 3d glasses, remote controls, gestural input devices, and sensor devices. built-in firmware adheres to the bluetooth human interface device (hid) profile and bluetooth device id pro file specifications. the cyw20730 radio has been designed to provide low power, low co st, and robust communications fo r applications operating in th e globally available 2.4 ghz unlicensed ism band. it is fu lly compliant with bluetooth radio specification 3.0. the single-chip bluetooth transceiver is a monolithic component implemented in a st andard digital cmos process and requires minimal external components to make a fully compliant bluetooth device. the cyw20730 is available in three package options: a 3 2- pin, 5 mm 5 mm qfn, a 40-pin, 6 mm 6 mm qfn, and a 64-pin, 7 mm 7 mm bga. cypress part numbering scheme cypress is converting the acquired iot part numbers from broadcom to the cypress par t numbering scheme. due to this conversion, there is no change in form, fit, or function as a result of offe ring the device with cypress part number marking. the table pro vides cypress ordering part number that matches an existing iot part number. table 1. mapping table for part number between broadcom and cypress broadcom part number cypress part number BCM20730 cyw20730 BCM20730a2kml2gt cyw20730a2kml2gt BCM20730a1kml2g cyw20730a1kml2g BCM20730a1kmlg cyw20730a1kmlg BCM20730a1kfbgt cyw20730a1kfbgt BCM20730a2kfbg cyw20730a2kfbg BCM20730a1kfbg cyw20730a1kfbg BCM20730a1kml2gt cyw20730a1kml2gt BCM20730a2kml2g cyw20730a2kml2g BCM20730a1kmlgt cyw20730a1kmlgt BCM20730a2kfbgt cyw20730a2kfbgt acronyms and abbreviations in most cases, acronyms and abbreviations are defined on first use. for a comprehensive list of acronyms and other terms used in cypress documents, go to http://www.cypress.com/glossary . applications wireless pointing devi ces: mice, trackballs , gestural controls wireless keyboards 3d glasses remote controls game controllers point-of-sale (pos) input devices remote sensors home automation personal health and fitness monitoring
cyw20730 document number: 002-14824 rev. *j page 2 of 50 features on-chip support for common keyboard and mouse interfaces eliminates external processor programmable keyscan matrix interface, up to 8 20 key- scanning matrix 3-axis quadrature signal decoder shutter control for 3d glasses infrared modulator ir learning triac control triggered broadcom fast connect supports adaptive frequency hopping excellent receiver sensitivity bluetooth specification 3.0 co mpatible, including enhanced power control (unicast connectionless data) bluetooth hid profile version 1.0 compliant bluetooth device id profile version 1.3 compliant bluetooth avrcp-ct profile version 1.3 compliant 10-bit auxiliary adc with 28 analog channels on-chip support for serial peripheral interface (master and slave modes) broadcom serial communications (bsc) interface (compatible with philips? (now nxp) i 2 c slaves) programmable output power contro l meets class 2 or class 3 requirements class 1 operation supported with external pa and t/r switch integrated arm cortex?-m3 based microprocessor core on-chip power-on reset (por) support for eeprom and serial flash interfaces integrated low-dropout regulator (ldo) on-chip software controlled power management unit three package types are available: 32-pin qfn package (5 mm 5 mm) 40-pin qfn package (6 mm 6 mm) 64-pin bga package (7 mm 7 mm) rohs compliant
cyw20730 document number: 002-14824 rev. *j page 3 of 50 figure 1. functi onal block diagram iot resources cypress provides a wealth of data at http://www.cypress.co m/internet-things-iot to help you to select the right iot device for your design, and quickly and effectively integrate the device into your design. cypress provides customer access to a wide range of information, including technical documentation, schematic diagra ms, product bill of materials, pcb layout information, and soft ware updates. customers can acquire technica l documentation and soft ware from the cypress support community website ? keyboard matrix scanner w/fifo 3-axis mouse signal controller processing unit (arm -cm3) system bus bluetooth baseband core 2.4 ghz radio rf control and data t/r switch rf i/o gpio control/ status registers frequency synthesizer 40 gpio on the 64-pin bga (22 gpio on the 40-pin qfn) (14 gpio on the 32-pin qfn) 24 mhz ref xtal pmu i/o ring bus i/o ring control registers peripheral interface block 1.2v vdd_core domain vdd_io domain wake 1.2v ldo 1.425v to 3.6v 1.2v vdd_core 320k rom 60k ram bsc/spi master interface (bsc is i 2 c- compa ? ble) sda/ mosi scl/ sck 6 quadrature inputs (3 pair) + high current driver controls 8 x 20 scan matrix 40 gpio 32 khz lpclk 28 adc inputs 24 mhz hclk (24 mhz to 1 mhz) autocal miso 1.2v vdd_rf domain pwm wdt 128 khz lpo 4 32 khz lpclk 128 khz lpclk 32 khz y?o~}??}vo power 1.62v to 3.6v vdd_io 1.2v por 1.2v test uart ir i/o ir mod. and learning spi m/s mia por 28 adc inputs ct gp adc vss, vddo, vddc periph uart uart_rxd uart_txd tx rx rts_n cts_n muxed on gpio volt. trans 3-d glasses and triac 1.62v to 3.6v
document number: 002-14824 rev. *j page 4 of 50 cyw20730 contents 1. functional description ................................................. 5 1.1 keyboard scanner ................................................. 5 1.2 mouse quadrature signal decoder ....................... 6 1.3 shutter control for 3d gl asses ............................. 6 1.4 infrared modulator ................................................. 7 1.5 infrared learning ................................................... 7 1.6 triac control .......................................................... 8 1.7 broadcom proprietary control signaling and ?
document number: 002-14824 rev. *j page 5 of 50 cyw20730 1. functional description 1.1 keyboard scanner the keyboard scanner is designed to autonomously sample keys and store them into buffer registers without the need for the host microcontroller to intervene. the scanner has the following features: ability to turn off its clock if no keys pressed. sequential scanning of up to 160 keys in an 8 x 20 matrix. programmable number of columns from 1 to 20. programmable number of rows from 1 to 8. 16-byte key-code buffer (can be augmented by firmware). 128 khz clock ? allows scanning of full 160-key matrix in about 1.2 ms. n-key rollover with selective 2-ke y lockout if ghost is detected. keys are buffered until host microcontroller has a chance to read it, or until overflow occurs. hardware debouncing and noise/glitch filtering. low-power consumption. single-digit a-level sleep current. 1.1.1 theory of operation the key scan block is controlled by a st ate machine with the following states: idle the state machine begins in the idle state. in this state, all column outputs are driven high. if any key is pressed, a transit ion occurs on one of the row inputs. this transition causes the 128 khz cl ock to be enabled (if it is not already enabled by another perip heral) and the state machine to enter the scan state. also in this stat e, an 8-bit row-hit register and an 8-bit key-index counter is reset to 0. scan in the scan state, a row counter counts from 0 up to a programma ble number of rows minus 1. once the last row is reached, the r ow counter is reset and the column counter is incremented. this cycle repeats until the row and co lumn counters are both at their respective terminal count values. at that point, the state machine moves into the scan-end state. as the keys are being scanned, the key-index counter is incremented. this counter is the value compared to the modifier key cod es stored, or in the key-code buffer if the key is not a modifier key. it can be used by the microprocessor as an index into a loo kup table of usage codes. also, as the n-th row is scanned, the row-hit register is ored with the current 8-bit row input values if the current column co ntains two or more row hits. during the scan of any column, if a key is det ected at the current row, and the row-hit register indicates th at a hit was detected in that same row on a previous column, then a ghos t condition may have occurred, and a bit in the status register is set to indicate this. scan end this state determines whether any keys were detected while in the scan state. if yes, the state machine returns to the scan sta te. if no, the state machine returns to the idle state, an d the 128 khz clock request signal is made inactive. the microcontroller can poll the key status register.
document number: 002-14824 rev. *j page 6 of 50 cyw20730 1.2 mouse quadrature signal decoder the mouse signal decoder is designed to autonomously sample two quadrature signals commonl y generated by optomechanical mouse apparatus. the decoder has the following features: three pairs of inputs for x, y, and z (typical sc roll wheel) axis signals. each axis has two options: for the x axis, choose p2 or p32 as x0 and p3 or p33 as x1. for the y axis, choose p4 or p34 as y0 and p5 or p35 as y1. for the z axis, choose p6 or p36 as z0 and p7 or p37 as z1. control of up to four external high current gpios to power external optoelectronics: turn-on and turn-off time can be staggered for each hc-gpio to avoid simultaneous switching of hi gh currents and having multipl e high-current devices on at the same time. sample time can be staggered for each axis. sense of the control signal can be active high or active low. control signal can be tristated for off condition or driven high or low, as appropriate. 1.2.1 theory of operation the mouse decoder block has four 16-bit pwms for controlling ex ternal quadrature devices and sampling the quadrature inputs at its core. the gpio signals may be used to control such items as leds, ex ternal ics that may emulate quadr ature signals, photodiodes, and photodetectors. 1.3 shutter control for 3d glasses the cyw20730, combined with t he cyw20702, provides full system support for 3d glasses on televisions. the cyw20702 gets frame synchronization signals from the tv, converts them into proprietary timing control messages, then passes these messages t o the cyw20730. the cyw20730 uses t hese messages to synchronize the shutter control for the 3d glasses with the television frames . the cyw20730 can provide up to four synchroni zed control signals for left and right eye shutter control. these four lines can o utput pulses with microsecond resolution for on and off timing. t he total cycle time can be set for any period up to 65535 msec. the pulses are synchronized to each other for left and right eye shutters. the cyw20730 seamlessly adjusts the timing of the control signal s based on control messages from the cyw20702, ensuring that the 3d glasses remain synchroni zed to the tv display frame. 3d hardware control on the cyw20730 works independently of th e rest of the system. the cyw 20730 negotiates sniff with the cyw20702 and, except for sniff resynchronization periods, most of the cyw20730 circuitry remains in a low power state while the 3d glasses subsystem continues to provide shutter timi ng and control pul ses. this significantly reduces total system power consumption. the cyw20730a2 has the new bt sig 3dg profile, as well as legacy m ode 3dg, included in rom. this allows it to support a smaller and lower cost external memory of 4 kb.
document number: 002-14824 rev. *j page 7 of 50 cyw20730 1.4 infrared modulator the cyw20730 includes hardware support for infrared tx. the ha rdware can transmit both modulated and unmodulated waveforms. for modulated waveforms, hardware inserts the desired carrier frequency into all ir transmissions. ir tx can be sourced from firmware-supplied descriptors, a programmable bit, or the peripheral uart transmitter. if descriptors are used, they include ir on/off state and the du ration between 1?32767 sec. the cyw20730 ir tx firmware driver inserts this information in a har dware fifo and makes sure that all descriptors are played out without a glitch due to underrun . see figure 2 . figure 2. infrared tx 1.5 infrared learning the cyw20730 includes hardware support for infrared learning. th e hardware can detect both modulated and unmodulated signals. for modulated signals, the cyw20730 can detect carrier frequencies between 10 khz and 500 khz and the duration that the signal is present or absent. the cyw20730 firmware driver supports fu rther analysis and compression of learned signal. the learned sig nal can then be played back through the cyw20730 ir tx subsystem. see figure 3 . figure 3. infrared rx
document number: 002-14824 rev. *j page 8 of 50 cyw20730 1.6 triac control the cyw20730 includes hardware support for zero-crossing detection and trigger control for up to four triacs. the cyw20730 dete cts zero-crossing on the ac zero detection line and uses that to prov ide a pulse that is offset from the zero-crossing. this allows the cyw20730 to be used in dimmer applications, as well as any other applications that require a cont rol signal that is offset from an input event. 1.7 broadcom proprietary control signaling and triggered broadcom fast connect broadcom proprietary control signaling (bpc s) and triggered broadcom fast connect (tbfc) are broadcom-proprietary baseband (acl) suspension and low latency reconnection mechanisms that re establish the baseband connecti on with the peer controller that also supports bpcs/tbfc. the cyw20730 uses bpcs primitives to allow a human interface de vice (hid) to suspend all rf traffic after a configurable idle period with no reportable activity. to conserve power, it can th en enter one of its low power st ates while still logically rema ining connected at the l2cap and hid la yers with the peer device. when an event requires the hid to deliver a report to the peer devi ce, the cyw20730 uses the tbfc and bpcs mech anisms to reestablish the baseband connec tion and can immediately resume l2cap traffic, greatly reducing latency between the event and delivery of the report to the peer device. certain applications may make use of the cyw20730 baseband fast connect (bfc) mechanism for power savings and lower latencies not achievable by using even long sniff intervals by co mpletely eliminating the need to maintain an rf link, while st ill being able to establish acl and l2cap connections much faster than regular methods. 1.8 bluetooth baseband core the bluetooth baseband core (bbc) implements all of the time-cri tical functions required for high performance bluetooth operati on. the bbc manages the buffering, segmentation, and data routing for all connections. it al so buffers data that passes through it, handles data flow control, schedules acl tx/rx transactions, monitors bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and compos es and decodes hci packets. in addition to these functions, i t independently handles hci event types and hci command types. the following transmit and receive functions are also implement ed in the bbc hardware to increase tx/rx data reliability and se curity before sending over the air: receive functions: symbol timing recovery, data deframing, forwar d error correction (fec), heade r error control (hec), cyclic redundancy check (crc), data dec ryption, and data dewhitening. transmit functions: data framing, fec generation, hec generat ion, crc generation, link key gen eration, data enc ryption, and data whitening. 1.8.1 frequency hopping generator the frequency hopping sequence generator selects the correct ho pping channel number depending on the link controller state, bluetooth clock, and device address. 1.8.2 e0 encryption the encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and provide minimal processor intervention. 1.8.3 link control layer the link control layer is part of the bluetooth link control fu nctions that are implemented in dedicated logic in the link cont rol unit (lcu). this layer consists of the command controller, which ta kes software commands, and other controllers that are activated o r configured by the command controller to perform the link c ontrol tasks. each task performs a different bluetooth link controlle r state. standby and connection are the tw o major states. in addition, th ere are five substates: page, page scan, inquiry, inquiry scan, and sniff. 1.8.4 adaptive frequency hopping the cyw20730 gathers link quality statistics on a channel-by-channe l basis to facilitate channel assessment and channel map selection. the link quality is determined by using both rf and ba seband signal processing to provide a more accurate frequency hop map.
document number: 002-14824 rev. *j page 9 of 50 cyw20730 1.8.5 bluetooth version 3.0 features the cyw20730 supports bluetooth 3.0, including the following options: enhanced power control unicast connectionless data hci read encryption key size command the cyw20730 also supports the follo wing bluetooth version 2.1 features: extended inquiry response sniff subrating encryption pause and resume secure simple pairing link supervision timeout changed event erroneous data reporting non-automatically-flushable packet boundary flag security mode 4 1.8.6 test mode support the cyw20730 fully supports bluetooth test mode, as described in part 1 of the bluetooth 3.0 spec ification. this includes the transmitter tests, normal and delayed loopback tests, and the reduced hopping sequence. in addition to the standard bluetooth test mode, the device supports enhanced testin g features to simplify rf debugging and qua li- fication as well as type-approval testing. 1.9 adc port the cyw20730 contains a 16-bit adc (effective number of bits is 10). additionally: there are 28 analog input channels in the 64-pin package, 12 analog input channels in the 40-pin package, and 9 analog input channels in the 32-pin package. all ch annels are multiplexed on various gpios. the conversion time is 10 ? ?
document number: 002-14824 rev. *j page 10 of 50 cyw20730 1.10 serial pe ripheral interface the cyw20730 has two independent spi interfaces . one is a master-only interface and the ot her can be either a master or a slave . each interface has a 16-byte transmit buffer and a 16-byte rece ive buffer. to support more flexibility for user applications, t he cyw20730 has optional i/o ports that can be configured individually and separately fo r each functional pin, as shown in ta b l e 3 . the cyw20730 acts as an spi master device that s upports 1.8v or 3.3v spi slaves, as shown in table 3 . the cyw20730 can also act as an spi slave device that supports a 1.8v or 3.3v spi master, as shown in table 3 . table 3. cyw20730 first spi set (master mode) pin name spi_clk spi_mosi spi_miso spi_cs a a. any gpio can be used as spi_cs when spi is in master mode. configuration set 1 scl sda p24 ? configuration set 2 scl sda p26 ? configuration set 3 (default for serial flash) scl sda p32 p33 configuration set 4 scl sda p39 ? table 4. cyw20730 second spi set (master mode) pin name spi_clk spi_mosi spi_miso spi_cs a configuration set 1 p3 p0 p1 ? configuration set 2 p3 p0 p5 ? configuration set 3 p3 p2 p1 ? configuration set 4 p3 p2 p5 ? configuration set 5 p3 p4 p1 ? configuration set 6 p3 p4 p5 ? configuration set 7 p3 p27 p1 ? configuration set 8 p3 p27 p5 ? configuration set 9 p3 p38 p1 ? configuration set 10 p3 p38 p5 ? configuration set 11 p7 p0 p1 ? configuration set 12 p7 p0 p5 ? configuration set 13 p7 p2 p1 ? configuration set 14 p7 p2 p5 ? configuration set 15 p7 p4 p1 ? configuration set 16 p7 p4 p5 ? configuration set 17 p7 p27 p1 ? configuration set 18 p7 p27 p5 ? configuration set 19 p7 p38 p1 ? configuration set 20 p7 p38 p5 ? configuration set 21 p24 p0 p25 ? configuration set 22 p24 p2 p25 ? configuration set 23 p24 p4 p25 ? configuration set 24 p24 p27 p25 ?
document number: 002-14824 rev. *j page 11 of 50 cyw20730 configuration set 25 p24 p38 p25 ? configuration set 26 p36 p0 p25 ? configuration set 27 p36 p2 p25 ? configuration set 28 p36 p4 p25 ? configuration set 29 p36 p27 p25 ? configuration set 30 p36 p38 p25 ? a. any gpio can be used as spi_cs when spi is in master mode. table 5. cyw20730 second spi set (slave mode) a pin name spi_clk spi_mosi spi_miso spi_cs configuration set 1 p3 p0 p1 p2 configuration set 2 p3 p0 p5 p2 configuration set 3 p3 p4 p1 p2 configuration set 4 p3 p4 p5 p2 configuration set 5 p7 p0 p1 p2 configuration set 6 p7 p0 p5 p2 configuration set 7 p7 p4 p1 p2 configuration set 8 p7 p4 p5 p2 configuration set 9 p3 p0 p1 p6 configuration set 10 p3 p0 p5 p6 configuration set 11 p3 p4 p1 p6 configuration set 12 p3 p4 p5 p6 configuration set 13 p7 p0 p1 p6 configuration set 14 p7 p0 p5 p6 configuration set 15 p7 p4 p1 p6 configuration set 16 p7 p4 p5 p6 configuration set 17 p24 p27 p25 p26 configuration set 18 p24 p33 p25 p26 configuration set 19 p24 p38 p25 p26 configuration set 20 p36 p27 p25 p26 configuration set 21 p36 p33 p25 p26 configuration set 22 p36 p38 p25 p26 configuration set 23 p24 p27 p25 p32 configuration set 24 p24 p33 p25 p32 configuration set 25 p24 p38 p25 p32 configuration set 26 p36 p27 p25 p32 configuration set 27 p36 p33 p25 p32 configuration set 28 p36 p38 p25 p32 table 4. cyw20730 second spi set (master mode) (cont.) pin name spi_clk spi_mosi spi_miso spi_cs a
document number: 002-14824 rev. *j page 12 of 50 cyw20730 1.11 microprocessor unit the cyw20730 microprocessor unit (pu) executes software from the link control (lc) layer up to the application layer component s that ensure adherence to the bluetooth huma n interface device (hid) profile and audio/ video remote control profile (avrcp). the microprocessor is based on an arm cortex?-m3, 32-bit risc processor with embedded ice-rt de bug and jtag interface units. the pu has 320 kb of rom for program storage and boot- up, 60 kb of ram for scratch-pad data, and patch ram code. the internal boot rom provides power-on reset flexibility, whic h enables the same device to be used in different hid applicatio ns with an external serial eeprom or with an extern al serial flash memory. at po wer-up, the lowest layer of the protocol stack is execu ted from the internal rom memory. external patches may be applied to the rom- based firmware to provide flexibility for b ug fixes and feature additions. the devic e can also support the integrati on of user applications. 1.11.1 eeprom interface the cyw20730 provides a broadcom serial control (bsc) master in terface. the bsc is programmed by the cpu to generate four types of bsc bus transfers: read-only, write-only, combined re ad/write, and combined write/read. bsc supports both low-speed an d fast mode devices. the bsc is compatible with a philips? (now nxp) i 2 c slave device, except that master arbitration (multiple i 2 c masters contending for the bus) is not supported. the eeprom can contain customer application configuration information including: app lication code, configuration data, patches, pairing information, bd_addr, baud rate, sdp service record, and file system information used for code. native support for the microchip? 24lc128, microchi p 24aa128, and st micro? m24128-br is included. 1.11.2 serial flash interface the cyw20730 includes an spi master controller that can be used to access serial flash memory. the spi master contains an ahb slave interface, transmit and receive fifos, and the spi core phy logic. devices natively supported include the following: atmel? at25bcm512b mxic? mx25v512zui-20g configuration set 29 p24 p27 p25 p39 configuration set 30 p24 p33 p25 p39 configuration set 31 p24 p38 p25 p39 configuration set 32 p36 p27 p25 p39 configuration set 33 p36 p33 p25 p39 configuration set 34 p36 p38 p25 p39 a. additional configuration se ts are available upon request. table 5. cyw20730 second spi set (slave mode) a pin name spi_clk spi_mosi spi_miso spi_cs
document number: 002-14824 rev. *j page 13 of 50 cyw20730 1.11.3 internal reset figure 4. internal reset timing 1.11.4 external reset the cyw20730 has an integrated power-on reset circuit that complete ly resets all circuits to a known power-on state. an externa l active low reset signal, reset_n, can be used to pu t the cyw20730 in the rese t state. the reset_n pin has an internal pull-up resistor and, in most applications, it does not require that anything be connected to it . reset_n should only be released after the vddo supply voltage level has been stabilized. figure 5. external reset timing vddo vddo ? por vddc vddo ? por ? threshold vddo ? por ? delay ~ ? 2 ? ms vddc ? por vddc ? por ? threshold vddc ? por ? delay ~ ? 2 ? ms baseband ? reset crystal ? warm \ up ? delay: ? ~ ? 5 ? ms crystal ? enable start ? reading ? eeprom ? and ? firmware ? boot reset_n pulse ? width >50 ? s crystal ? enable baseband ? reset start ? reading ? eeprom ? and ? firmware ? boot crystal ? warm \ up ? delay: ? ~ ? 5 ? ms
document number: 002-14824 rev. *j page 14 of 50 cyw20730 1.12 integrated radio transceiver the cyw20730 has an integrat ed radio transceiver that is optimized for 2.4 gh z bluetooth? wireless systems. it has been designe d to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 ghz unlicens ed ism band. it is fully compliant with blueto oth radio specification 3.0 and meets or e xceeds the requirements to provide the hig hest communication link quality of service. 1.12.1 transmitter path the cyw20730 features a fully integrated transmitter. the baseb and transmit data is gfsk modulated in the 2.4 ghz ism band. digital modulator the digital modulator performs the data modulation and filter ing required for the gfsk signal. the fully digital modulator mini mizes any frequency drift or anomalies in the modulati on characteristics of the transmitted signal. power amplifier the cyw20730 has an integrated power amplifier (pa) t hat can transmit up to +4 dbm for class 2 operation. 1.12.2 receiver path the receiver path uses a low if scheme to downconvert the re ceived signal for demodulation in the digital demodulator and bit synchronizer. the receiver path provides a high degree of lin earity, an extended dynamic range, and high-order, on-chip channel filtering to ensure reliable oper ation in the noisy 2.4 ghz ism band. the front- end topology, which has built-in out-of-band at tenuation, enables the cyw20730 to be used in most applications without off-chip filtering. digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit synchronization algorithm. receiver signal strength indicator the radio portion of the cyw20730 provides a receiver signal st rength indicator (rssi) to the baseband. this enables the contro ller to take part in a bluetooth power-controlled link by providing a me tric of its own receiver signal strength to determine whethe r the transmitter should increase or decrease its output power. 1.12.3 local oscillator the local oscillator (lo) provides fast frequency hopping (1 600 hops/second) across the 79 maximum available channels. the cyw20730 uses an internal loop filter. 1.12.4 calibration the cyw20730 radio transceiver features a self-contained automate d calibration scheme. no user interaction is required during normal operation or during manufacturing to provide optimal pe rformance. calibration compensates for filter, matching network, and amplifier gain and phase characteristics to yi eld radio performance within 2% of what is optimal. calibration takes process and temperature variations into account, and it takes place transparently during normal oper ation and hop setting times. 1.12.5 internal ldo regulator the cyw20730 has an integrated 1.2v ldo regulator that provides power to the digital and rf circuits. the 1.2v ldo regulator operates from a 1.425v to 3.63v input supply with a 30 ma maximum load current. note: always place the decoupling capacitors near the pins as closely together as possible.
document number: 002-14824 rev. *j page 15 of 50 cyw20730 1.13 peripheral transport unit 1.13.1 broadcom serial communications interface the cyw20730 provides a 2-pin master bsc interface, which can be used to retrieve configuration information from an external eeprom or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ics used in mouse devices. the bsc interface is compatible with i 2 c slave devices. the bsc does not support multimaster capability or flexible wait- state insertion by either master or slave devices. the following transfer clock rates are supported by the bsc: 100 khz 400 khz 800 khz (not a standard i 2 c-compatible speed.) 1 mhz (compatibility with high-speed i 2 c-compatible devices is not guaranteed.) the following transfer types are supported by the bsc: read (up to 16 bytes can be read.) write (up to 16 bytes can be written.) read-then-write (up to 16 bytes can be re ad and up to 16 bytes can be written.) write-then-read (up to 16 bytes can be written and up to 16 bytes can be read.) hardware controls the transfers, requiring minimal firmware setup and supervision. the clock pin (scl) and data pin (sda) are both open-drain i/o pins. pull -up resistors external to the cyw20730 are required on both the scl and sda pins for proper operation. 1.13.2 uart interface the uart is a standard 2-wire interface (rx and tx) and has adj ustable baud rates from 9600 bps to 1.5 mbps. the baud rate can be selected via a vendor-specific uart hci command. the interface supports the bluetoot h 3.0 uart hci (h5) specification. the default baud rate for h5 is 115.2 kbaud. both high and low baud rates can be supported by running the uart clock at 24 mhz. the cyw20730 uart operates correctly with t he host uart as long as the combined baud rate error of the two devices is within 5 %. 1.14 clock frequencies the cyw20730 is set with crystal frequency of 24 mhz. 1.14.1 crystal oscillator the crystal oscillator requires a crystal with an accuracy of 20 ppm as defined by the bluetooth specification. two external l oad capacitors in the range of 5 pf to 30 pf are required to work with the crystal oscillator. the selection of the load capacitors is crystal dependent. table 6 on page 16 shows the recommended crystal specification. figure 6. recommended oscillator configuration ? 12 pf load crystal 22 ? pf 20 ? pf crystal xin xout
? ? 24.000 ? mhz ? fundamental ? @25c ? 10 ? ppm @0c to +70c ? 10 ? ppm ? ? ? 50 w ? ? 12 ? pf ? 0 ? +70 c ? ?40 ? +125 c ? ? ? 200 ? w ? ? ? 10 ppm/year ? ? ? 2 pf document number: 002-14824 rev. *j page 16 of 50 cyw20730 hid peripheral block the peripheral blocks of t he cyw20730 all run from a single 128 khz low-power rc oscillator. the oscillator can be turned on at the request of any of the peripherals. if the peripheral is not enabled, it shall not assert its clock request line. the keyboard scanner is a special case in that it may drop its clock request line even when enabled and then reassert the clock request line if a keypress is detected. 32 khz crystal oscillator figure 7 shows the 32 khz crystal (xtal) oscillator with external components and table 7 on page 17 lists the oscillator?s character- istics. it is a standard pierce oscillator using a comparator wit h hysteresis on the output to create a single-ended digital ou tput. the hysteresis was added to eliminate any chatter when the input is around the threshold of the comparator and is ~100 mv. this cir cuit can be operated with a 32 khz or 32.768 khz crystal oscillator or be driven with a clock input at similar frequency. the defaul t component values are: r1 = 10 m ? , c1 = c2 = ~10 pf. the values of c1 and c2 are used to fine-tune the oscillator. figure 7. 32 khz osci llator block diagram table 6. reference crystal electrical specifications parameter conditions minimum typical maximum unit nominal frequency oscillation mode frequency tolerance tolerance stability over temp equivalent series resistance load capacitance operating temperature range storage temperature range drive level aging shunt capacitance c2 c1 r1 32.768 khz xtal
document number: 002-14824 rev. *j page 17 of 50 cyw20730 1.15 gpio port the cyw20730 has 14 general-purpose i/os (gpios) in the 32-pin pa ckage, 22 gpios in the 40-pin package, and 40 gpios in the 64-pin package. all gpios support programmable pull-up and pull-down resistors, and all support a 2 ma drive strength except p2 6, p27, p28, and p29, which provide a 16 ma drive strength at 3.3v supply. 1.15.1 port 0?port 1, port 8?port 23, and port 28?port 38 all of these pins can be programmed as adc inputs. 1.15.2 port 26?port 29 p[26:29] consists of four pins. all pins are capable of sinking up to 16 ma for led. these pins also have the pwm function, whi ch can be used for led dimming. table 7. xtal oscillator characteristics parameter symbol conditions minimum typical maximum unit output frequency f oscout ? ? 32.768 ? khz frequency tolerance ? crystal dependent ? 100 ? ppm start-up time t startup ? ? ? 500 ms xtal drive level p drv for crystal selection 0.5 ? ? ? ?
document number: 002-14824 rev. *j page 18 of 50 cyw20730 1.16 pwm the cyw20730 has four internal pwm channels. the pwm module consists of the following: pwm1?4 each of the four pwm channels, pwm 1?4, contains the following registers: 10-bit initial value register (read/write) 10-bit toggle register (read/write) 10-bit pwm counter value register (read) the pwm configuration register is shared among pw m1?4 (read/write). this 12-bit register is used: to configure each pwm channel. to select the clock of each pwm channel to change the phase of each pwm channel figure 8 shows the structure of one pwm channel. figure 8. pwm channel block diagram pwm_cfg_adr ? register pwm#_init_val_adr ? register pwm#_togg_val_adr ? register pwm#_cntr_adr enable cntr ? value ? is ? cm3 ? readable clk_sel o_flip 10'h000 10'h3ff 10 10 10 example: ? pwm ? cntr ? w/ ? pwm#_init_val ? = ? 0 ? (dashed ? line) pwm ? cntr ? w/ ? pwm#_init_val ? = ? x ? (solid ? line) ?????????????????? 10'hx pwm_out pwm_togg_val_adr pwm_out
document number: 002-14824 rev. *j page 19 of 50 cyw20730 1.17 power management unit the power management unit (pmu) provides power management features that can be invoked by software through power management registers or packet-handling in the baseband core. 1.17.1 rf power management the bbc generates power-down control signals for the transmit path, receive path, pll, and power amplifier to the 2.4 ghz trans - ceiver, which then processes the power-down functions accordingly. 1.17.2 host controller power management power is automatically managed by the firmware based on input dev ice activity. as a power-saving task, the firmware controls th e disabling of the on-chip regulator when in deep sleep mode. 1.17.3 bbc power management there are several low-power operations for the bbc: physical layer packet handling turns rf on and off dynamically within packet tx and rx. bluetooth-specified low-power connection sniff mode. while in these low-power connection modes, the cyw20730 runs on the low power oscillator and wakes up after a predefined time period. the cyw20730 automatically adjusts its pow er dissipation based on user activity. the following power modes are supported: active mode idle mode sleep mode hidoff mode the cyw20730 transitions to the next lower state after a programm able period of user inactivity. busy mode is immediately enter ed when user activity resumes. in hidoff mode, the cyw20730 baseband and core are powered off by disabling power to ldoout. the vddo domain remains powered up and will turn the remainder of the chip on when it det ects user events. this mode mini mizes chip power consumption a nd is intended for long periods of inactivity.
document number: 002-14824 rev. *j page 20 of 50 cyw20730 2. pin assignments 2.1 pin descriptions table 8. pin descriptions pin number pin name i/o power domain description 32-pin qfn 40-pin qfn 64-pin bga radio i/o 6 8 f1 rf i/o vdd_rf rf antenna port rf power supplies 4 6 d1 vddif i vdd_rf ifpll power supply 5 7 e1 vddfe i vdd_rf rf front-end supply 7 9 h1 vddvco i vdd_rf vco, logen supply 8 10 h2 vddpll i vdd_rf rfpll and crystal oscillator supply power supplies 11 13 h6 vddc i n/a baseband core supply ? ? d4, e2, e5, f2, g1, g2 vss i n/a ground 28 34 a6, d7 vddo i vddo i/o pad and core supply 14 16 ? vddm i vddm i/o pad supply clock generator and crystal interface 9 11 h3 xtali i vdd_rf crystal oscillator input. see ?crystal oscillator? on page 15 for options. 10 12 g3 xtalo o vdd_rf crystal oscillator output. 1 40 a3 xtali32k i vddo low-power oscillator (lpo) input is used. alternative function: p11 and p27 in 32-qfn only p11 in 40-qfn only p39 in 64-bga only 32 39 b3 xtalo32k o vddo low-power oscillator (lpo) output. alternative function: p12 and p26 in 32-qfn only p12 in 40-qfn only p38 in 64-bga only core 18 20 g8 reset_n i/o pu vddo active-low system rese t with open-drain output & internal pull-up resistor 17 19 g7 tmc i vddo test mode control high: test mode connect to gnd if not used.
document number: 002-14824 rev. *j page 21 of 50 cyw20730 uart 12 14 h5 uart_rxd i vddm a uart serial input ? serial data input for the hci uart interface. leave uncon- nected if not used. alternative function: gpio3 13 15 g5 uart_txd o, pu vddm a uart serial output ? serial data output for the hci uart interface. leave unconnected if not used. alternative function: gpio2 bsc 15 17 f7 sda i/o, pu vddm a data signal for an external i 2 c device. alternative function: spi_1: mosi (master only) gpio0 cts 16 18 e8 scl i/o, pu vddm a clock signal for an external i 2 c device. alternative function: spi_1: spi_clk (master only) gpio1 rts ldo regulator power supplies 2 4 b1 ldoin i ldo battery input supply for the ldo 3 5 c1 ldoout o ldo ldo output a. vddo for 64-pin package. table 8. pin descriptions (cont.) pin number pin name i/o power domain description 32-pin qfn 40-pin qfn 64-pin bga
document number: 002-14824 rev. *j page 22 of 50 cyw20730 table 9. gpio pin descriptions a pin number pin name default di- rection after por power domain alternate function description 32-pin qfn 40-pin qfn 64-pin bga 19 21 f6 p0 input floating vddo gpio: p0 keyboard scan input (row): ksi0 a/d converter input peripheral uart: puart_tx spi_2: mosi (master and slave) ir_rx 60 hz_main not available during tmc=1 20 22 g6 p1 input floating vddo gpio: p1 keyboard scan input (row): ksi1 a/d converter input peripheral uart: puart_rts spi_2: miso (master and slave) ir_tx 22 24 h8 p2 input floating vddo gpio: p2 keyboard scan input (row): ksi2 quadrature: qdx0 peripheral uart: puart_rx triac control 2 spi_2: spi_cs (slave only) spi_2: spi_mosi (master only) 21 23 f8 p3 input floating vddo gpio: p3 keyboard scan input (row): ksi3 quadrature: qdx1 peripheral uart: puart_cts spi_2: spi_clk (master and slave) 23 25 h7 p4 input floating vddo gpio: p4 keyboard scan input (row): ksi4 quadrature: qdy0 peripheral uart: puart_rx spi_2: mosi (master and slave) ir_tx
document number: 002-14824 rev. *j page 23 of 50 cyw20730 ? 26 e6 p5 input floating vddo gpio: p5 keyboard scan input (row): ksi5 quadrature: qdy1 peripheral uart: puart_tx spi_2: miso (master and slave) ? 27 f5 p6 pwm2 input floating vddo gpio: p6 keyboard scan input (row): ksi6 quadrature: qdz0 peripheral uart: puart_rts spi_2: spi_cs (slave only) 60hz_main triac control 1 ? 28 c5 p7 input floating vddo gpio: p7 keyboard scan input (row): ksi7 quadrature: qdz1 peripheral uart: puart_cts spi_2: spi_clk (master and slave) 24 29 f4 p8 input floating vddo gpio: p8 keyboard scan output (column): kso0 a/d converter input external t/r switch control: ~tx_pd alternative function: p33 in 32-qfn only ? 3 a1 p9 input floating vddo gpio: p9 keyboard scan output (column): kso1 a/d converter input external t/r switch control: tx_pd ? 2 d2 p10 pwm3 input floating vddo gpio: p10 keyboard scan output (column): kso2 a/d converter input 1 40 c2 p11 input floating vddo gpio: p11 keyboard scan output (column): kso3 a/d converter input xtali32k (32-qfn and 40-qfn only) alternative function: p27 in 32-qfn only table 9. gpio pin descriptions a (cont.) pin number pin name default di- rection after por power domain alternate function description 32-pin qfn 40-pin qfn 64-pin bga
document number: 002-14824 rev. *j page 24 of 50 cyw20730 32 39 b2 p12 input floating vddo gpio: p12 keyboard scan output (column): kso4 a/d converter input xtalo32k (32-qfn and 40-qfn only) alternative function: p26 in 32-qfn only 29 35 f3 p13 pwm3 input floating vddo gpio: p13 keyboard scan output (column): kso5 a/d converter input triac control 3 alternative function: p28 in 32-qfn only 30 36 d3 p14 pwm2 input floating vddo gpio: p14 keyboard scan output (column): kso6 a/d converter input triac control 4 alternative function: p38 in 32-qfn only 31 37 a2 p15 input floating vddo gpio: p15 keyboard scan output (column): kso7 a/d converter input ir_rx 60hz_main ? ? c8 p16 input floating vddo gpio: p16 keyboard scan output (column): kso8 ? ? h4 p17 input floating vddo gpio: p17 keyboard scan output (column): kso9 a/d converter input ? ? c7 p18 input floating vddo gpio: p18 keyboard scan output (column): kso10 a/d converter input ? ? b8 p19 input floating vddo gpio: p19 keyboard scan output (column): kso11 a/d converter input ? ? a8 p20 input floating vddo gpio: p20 keyboard scan output (column): kso12 a/d converter input table 9. gpio pin descriptions a (cont.) pin number pin name default di- rection after por power domain alternate function description 32-pin qfn 40-pin qfn 64-pin bga
document number: 002-14824 rev. *j page 25 of 50 cyw20730 ? ? c6 p21 input floating vddo gpio: p21 keyboard scan output (column): kso13 a/d converter input triac control 3 ? ? g4 p22 input floating vddo gpio: p22 keyboard scan output (column): kso14 a/d converter input triac control 4 ? ? e3 p23 input floating vddo gpio: p23 keyboard scan output (column): kso15 a/d converter input 27 33 a7 p24 input floating vddo gpio: p24 keyboard scan output (column): kso16 spi_2: spi_clk (master and slave) spi_1: miso (master only) peripheral uart: puart_tx 26 32 b7 p25 input floating vddo gpio: p25 keyboard scan output (column): kso17 spi_2: miso (master and slave) peripheral uart: puart_rx 32 38 a4 p26 pwm0 input floating vddo gpio: p26 keyboard scan output (column): kso18 spi_2: spi_cs (slave only) spi_1: miso (master only) optical control output: qoc0 triac control 1 alternative function: p12 in 32-qfn only current: 16 ma 1 1 b4 p27 pwm1 input floating vddo gpio: p27 keyboard scan output (column): kso19 spi_2: mosi (master and slave) optical control output: qoc1 triac control 2 alternative function: p11 in 32-qfn only current: 16 ma table 9. gpio pin descriptions a (cont.) pin number pin name default di- rection after por power domain alternate function description 32-pin qfn 40-pin qfn 64-pin bga
document number: 002-14824 rev. *j page 26 of 50 cyw20730 29 ? b5 p28 pwm2 input floating vddo gpio: p28 optical control output: qoc2 a/d converter input led1 ir_tx alternative function: p13 in 32-qfn only current: 16 ma ? ? a5 p29 pwm3 input floating vddo gpio: p29 optical control output: qoc3 a/d converter input led2 ir_rx current: 16 ma ? ? e4 p30 input floating vddo gpio: p30 a/d converter input pairing button pin in default fw peripheral uart: puart_rts ? ? e7 p31 input floating vddo gpio: p31 a/d converter input eeprom wp pin in default fw peripheral uart: puart_tx 25 31 d6 p32 input floating vddo gpio: p32 a/d converter input quadrature: qdx0 spi_2: spi_cs (slave only) spi_1: miso (master only) auxiliary clock output: aclk0 peripheral uart: puart_tx 24 30 d8 p33 input floating vddo gpio: p33 a/d converter input quadrature: qdx1 spi_2: mosi (slave only) auxiliary clock output: aclk1 peripheral uart: puart_rx alternative function: p8 in 32-qfn only table 9. gpio pin descriptions a (cont.) pin number pin name default di- rection after por power domain alternate function description 32-pin qfn 40-pin qfn 64-pin bga
document number: 002-14824 rev. *j page 27 of 50 cyw20730 ? ? b6 p34 input floating vddo gpio: p34 a/d converter input quadrature: qdy0 peripheral uart: puart_rx external t/r switch control: tx_pd ? ? d5 p35 input floating vddo gpio: p35 a/d converter input quadrature: qdy1 peripheral uart: puart_cts ? ? c4 p36 input floating vddo gpio: p36 a/d converter input quadrature: qdz0 spi_2: spi_clk (master and slave) auxiliary clock output: aclk0 battery detect pin in default fw external t/r switch control: ~tx_pd ? ? c3 p37 input floating vddo gpio: p37 a/d converter input quadrature: qdz1 spi_2: miso (slave only) auxiliary clock output: aclk1 30 ? b3 p38 input floating vddo gpio: p38 a/d converter input spi_2: mosi (master and slave) ir_tx xtalo32k (64-bga only) alternative function: p14 in 32-qfn only ? ? a3 p39 input floating vddo gpio: p39 spi_2: spi_cs (slave only) spi_1: miso (master only) infrared control: ir_rx external pa ramp control: pa_ramp xtali32k (64-bga only) 60hz_main a. during power-on reset, all inputs are disabled. table 9. gpio pin descriptions a (cont.) pin number pin name default di- rection after por power domain alternate function description 32-pin qfn 40-pin qfn 64-pin bga
document number: 002-14824 rev. *j page 28 of 50 cyw20730 2.2 ball maps figure 9. 32-pin qfn ball map 1 2 3 4 5 6 7 8 9 10111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p11/p27/xtali32k ldo_in ldo_out vddif vddfe rf vddvco vddpll xtali xtalo vddc uart_rxd uart_txd vddm sda scl tmc rst_n p0 p1 p3 p2 p4 p8/p33 p32 p25 p24 vddo p13/p28 p14/p38 p15 p12/p26/xtalo32k
document number: 002-14824 rev. *j page 29 of 50 cyw20730 figure 10. 40-pin qfn ball map 1 p27/pwm1 p10 p9 ldoin ldoout vddif vddfe rf vddvco vddpll 2 3 4 5 6 7 8 9 10 xtali xtalo vddc uart_rxd uart_txd vddm sda scl tmc reset_n 11 12 13 14 15 16 17 18 19 20 p33 p8 p7 p6 p5 p4 p2 p3 p1 p0 30 29 28 27 26 25 24 23 22 21 xtali32k/p11 xtalo32k/p12 p26/pwm0 p15 p14 p13 vddo p24 p25 p32 40 39 38 37 36 35 34 33 32 31
document number: 002-14824 rev. *j page 30 of 50 cyw20730 figure 11. 64-pin bga ball map p9 p15 p39/ xtali32k p26/ pwm0 p29/ pwm3 vddo p24 p20 ldoin p12 p38/ xtalo32k p27/ pwm1 p28/ pwm2 p34 p25 p19 ldoout p11 p37 p36 p7 p21 p18 p16 vddif p10 p14 vss p35 p32 vddo p33 vddfe vss p23 p30 vss p5 p31 scl rf vss p13 p8 p6 p0 sda p3 vss vss xtalo p22 uart_ txd p1 tmc reset _n vddvco vddpll xtali p17 uart_ rxd vddc p4 p2 a b c d e f g h 12345678 12345678 e f g h a b c d
? 1.4 v ? 1.4 v ? 3.8 v ? 3.8 v ? 3.8 v ? 1.4 v ? v ss ? 0.3 to v dd + 0.3 v to p r 0 to +70 c ts t g ?40 to +125 c 1.14 1.2 1.26 v 1.14 1.2 1.26 v 1.62 ? 3.63 v 1.62 ? 3.63 v 1.425 ? 3.63 v 1.14 1.2 b 1.26 v ? ? 100 mv ? ? 100 mv document number: 002-14824 rev. *j page 31 of 50 cyw20730 3. specifications 3.1 electrical characteristics table 10 shows the maximum electrical rating for voltages referenced to vdd pin. ta b l e 11 shows the power supply characteristics for the range t j = 0 to 125c. table 10. maximum electrical rating rating symbol value unit dc supply voltage for rf domain dc supply voltage for core domain dc supply voltage for vddm domain (uart/i 2 c) dc supply voltage for vddo domain dc supply voltage for vr3v dc supply voltage for vddfe voltage on input or output pin operating ambient te mperature range storage temperature range table 11. power supply parameter minimum a a. overall performance degrades beyond minimum and maximum supply voltages. typical maximum a unit dc supply voltage for rf dc supply voltage for core dc supply voltage for vddm (uart/i 2 c) dc supply voltage for vddo dc supply voltage for ldoin dc supply voltage for vddfe b. 1.2v for class 2 output with internal vreg. supply noise for vddo (peak-to-peak) supply noise for ldoin (peak-to-peak)
? 1.425 ? 3.63 v ? ? 1.2 ? v 0.8 ? 1.4 v ? 40 or 80 ? mv ?5 ? +5 % ? ? ? 30 ma ?0.2 ? 0.2 %v o /v ? 0.1 0.2 %v o /ma ? 6 ? a ? 5 200 na document number: 002-14824 rev. *j page 32 of 50 cyw20730 table ? ? ? ? ? ? ? ? ? ? table 12. ldo regulator electrical specifications parameter conditions min typ max unit input voltage range default output voltage output voltage ran ge step size accuracy at any step load current line regulation vin from 1.425 to 3.63v, i load = 30 ma load regulation i load from 1 a to 30 ma, vin = 3.3v, bonding r = 0.3 : quiescent current no load @vin = 3.3v *current limit enabled power-down current vin = 3.3v, worst@70c table 13. adc specifications parameter symbol conditions min typ max unit adc characteristics number of input channels ?? ?28?? channel switching rate f ch ? ? ? 133.33 kch/s input signal range v inp ?0 ? 3 . 6 3 v reference settling time ? changing refsel 7.5 ? ? p s input resistance r inp effective, single-ended ? 500 ? k : input capacitance c inp ?? ?5 p f conversion rate f c ? 5.859 ? 187 khz conversion time t c ? 5.35 ? 170.7 p s resolution r ? ? 16 ? bits effective number of bits ? ? ? see table 2 on page 9 ? absolute voltage measurement error ? using on-chip adc firmware driver ? 2 ? % current i i avdd1p2 + i avdd3p3 ?? 1m a power p ? ? 1.5 ? mw leakage current i leakage t = 25c ? ? 100 na power-up time t powerup ? ? ? 200 p s integral nonlinearity 3 inl ? ?1 ? 1 lsb a a. lsbs are expressed at the 10-bit level. differential nonlinearity a dnl ? ?1 ? 1 lsb a
v il ? ? 0.4 v v ih 0.75 vddo ? ? v v il ? ? 0.4 v v ih 1.2 ? ? v v ol ? ? 0.4 v v oh vddo ? 0.4 ? ? v c in ? 0.12 ? pf document number: 002-14824 rev. *j page 33 of 50 cyw20730 caution: this device is susceptible to permanent damage from electrosta tic discharge (esd). proper pr ecautions are required during handling and mounting to avoid excessive esd. table 14. digital level a a. this table is also applicable to vddmem domain. characteristics symbol min typ max unit input low voltage input high voltage input low voltage (vddo = 1.62v) input high voltage (vddo = 1.62v) output low voltage b b. at the specified drive current for the pad. output high voltage b input capacitance (vddmem domain) table 15. current consumption a a. current consumption measurements are taken at vbat with the assumption that vbat is connected to vddio and ldoin. operational mode conditions typ max unit receive receiver and baseband are both operating, 100% on. ? 26.6 ma transmit transmitter and baseband are both operating, 100% on. ? 24 at 2 dbm, 19 at 0 dbm ma dm1 average current when the device is in the transmit state, 100% utilization of available slots. 15.2 ? ma dh1 average current when the device is in the receive state, 100% utilization of available slots. 16.67 ? ma sleep internal lpo is in use. 28.4 ? ? a hidoff ? 1.5 ? ? a sniff mode, 11.25 ms slave 2.8 ? ma sniff mode, 22.5 ms slave 1.27 ? ma sniff mode, 60 ms slave 750 ? ? a sniff mode, 100 ms slave 500 ? ? a sniff mode, 495 ms slave 125 ? ? a table 16. esd tolerance model tolerance human body model (hbm) 2000v charged device model (cdm) 400v machine model (mm) 150v
document number: 002-14824 rev. *j page 34 of 50 cyw20730 3.2 rf specifications table 17. receiver rf specifications parameter mode and conditions min typ max unit receiver section frequency range ? 2402 ? 2480 mhz rx sensitivity (standard) gfsk, 0.1%ber, 1 mbps ? ?88.0 ?84.0 dbm rx sensitivity (low current) ? ?84.0 ? dbm input ip3 ? ?16 ? ? dbm maximum input ? ?10 ? ? dbm interference performance c/i cochannel gfsk, 0.1%ber a a. desired signal is 10 db above the referenc e sensitivity level (defined as ?70 dbm). ??11.0db c/i 1 mhz adjacent channel gfsk, 0.1%ber a ??0.0db c/i 2 mhz adjacent channel gfsk, 0.1%ber a ? ? ?30.0 db c/i ??
2402 ? 2480 mhz ?6.0 ? 4.0 dbm ? 4.0 ? dbm ? 2.0 ? db ? 900 1000 khz ? ? ?20 dbm ? ? ?40 dbm ? ? ?36.0 dbm ? ? ?30.0 dbm ? ? ?47.0 dbm ? ? ?47.0 dbm ? ? 75 khz ? ? 25 khz ? ? 40 khz ? ? 40 khz ? ? 20 khz/50 s 140 ? 175 khz 115 ? ? khz ? 1 ? mhz document number: 002-14824 rev. *j page 35 of 50 cyw20730 table 18. transmitter rf specifications parameter min typ max unit transmitter section frequency range output power adjustment range default output power output power variation 20 db bandwidth adjacent channel power |m ? n| = 2 |m ? n| ?? 3 out-of-band spurious emission 30 mhz to 1 ghz 1 ghz to 12.75 ghz 1.8 ghz to 1.9 ghz 5.15 ghz to 5.3 ghz lo performance initial carrier frequency tolerance frequency drift dh1 packet dh3 packet dh5 packet drift rate frequency deviation a verage deviation in payload (sequence used is 00001111) maximum deviation in payload (sequ ence used is 10101010) channel spacing
1 ? 24 baud out cycles 2 ? 10 ns 3 ? 2 baud out cycles document number: 002-14824 rev. *j page 36 of 50 cyw20730 3.3 timing and ac characteristics in this section, use th e numbers listed in the reference column of each table to interp ret the following timing diagrams. 3.3.1 uart timing figure 12. uart timing table 19. uart timi ng specifications reference characteristics min max unit delay time, uart_cts_n low to uart_txd valid setup time, uart_cts_n high before midp oint of stop bit delay time, midpoint of stop bit to uart_rts_n high
document number: 002-14824 rev. *j page 37 of 50 cyw20730 3.3.2 spi timing the spi interface supports clock speeds up to 12 mhz with vddio ? ? ? ? mosi 1 2 3 4 sclk mode ? 1 miso cs 5 invalid ? bit msb msb lsb lsb 6 sclk mode ? 3
1 tds_mo ? 41 ? ns 2 tdh_mo ? 120 ? ns 3 tds_mi ? tbd ? ns 4 tdh_mi ? tbd ? ns 5 c ts u _ c s ? sclk period ? 1 ? ? ns 6 c thd_cs ? sclk period ? ? ns 1 tds_mo ? 26 ? ns 2 tdh_mo ? 56 ? ns 3 tds_mi ? tbd ? ns 4 tdh_mi ? tbd ? ns 5 c tsu_cs ? sclk period ? 1 ? ? ns 6 c thd_cs ? sclk period ? ? ns document number: 002-14824 rev. *j page 38 of 50 cyw20730 table 21. spi1 timing values ? sclk = 6 mhz and vddm = 1.62v a reference characteristics symbol min typical b max unit output setup time, from mosi data valid to sample edge of sclk output hold time, from sample ? ed ge of sclk to mosi data update input setup time, from miso ? da ta valid to sample edge of sclk input hold time, from sample ? ed ge of sclk to miso data update time from cs assert to first sclk edge time from first sclk edge to cs de assert a. the sclk period is based on the limitation of tds_mi. sclk is designed for a maximum speed of 6 mhz. the speed can be adjuste d to as low as 400 hz by configuring the firmware. b. typical timing based on 20 pf/1 m ? load and sclk = 6 mhz. c. cs timing is firmware controlled. table 22. spi2 timing values ? sclk = 12 mhz and vddm = 3.2v a a. the sclk period is based on the limitation of tds_mi. sclk is designed for a maximum speed of 12 mhz. the speed can be adjust ed to as low as 400 hz by configuring the firmware. reference characteristics symbol min typical b b. typical timing based on 20 pf//1 m ? load and sclk = 12 mhz. max unit output setup time, from mosi ? data valid to sample edge of sclk output hold time, from sample ? ed ge of sclk to mosi data update input setup time, from miso ? da ta valid to sample edge of sclk input hold time, from sample ? ed ge of sclk to miso data update c. cs timing is firmware controlled in master mode and can be adjusted as required in slave mode. time from cs assert to first sclk edge time from first sclk edge to cs de assert
document number: 002-14824 rev. *j page 39 of 50 cyw20730 table 23. spi2 timing values ? sclk = 6 mhz and vddm = 1.62v a reference characteristics symbol min typical b max unit 1 output setup time, from mosi ? ? ? ? ?
1 ? 100 khz 400 800 1000 2 650 ? ns 3 280 ? ns 4 650 ? ns 5 280 ? ns 6 0 ? ns 7 100 ? ns 8 280 ? ns 9 ? 400 ns 10 650 ? ns document number: 002-14824 rev. *j page 40 of 50 cyw20730 3.3.3 bsc interface timing figure 14. bsc interface timing diagram table 24. bsc interface timing specifications reference characteristics min max unit clock frequency start condition setup time start condition hold time clock low time clock high time data input hold time a a. as a transmitter, 300 ns of delay is provided to bridge t he undefined region of the falling edge of scl to avoid unintended g eneration of start or stop conditions. data input setup time stop condition setup time output valid from clock bus free time b b. time that the cbus must be fr ee before a new transaction can start.
document number: 002-14824 rev. *j page 41 of 50 cyw20730 4. mechanical information figure 15. 32-pin qfn package
document number: 002-14824 rev. *j page 42 of 50 cyw20730 figure 16. 40-pin qfn package
document number: 002-14824 rev. *j page 43 of 50 cyw20730 figure 17. 64-pin fbga package
2500 pieces 13 inches 7 inches 12 mm 8 mm document number: 002-14824 rev. *j page 44 of 50 cyw20730 4.1 tape reel and packaging specifications the top left corner of the cyw20730 package is si tuated near the sprocket holes, as shown in figure 18 . figure 18. pin 1 orientation table 25. cyw20730 5 5 1 mm qfn, 32-pin tape reel specifications parameter value quantity per reel reel diameter hub diameter tape width tape pitch table 26. cyw20730 6 6 1 mm qfn, 40-pin tape reel specifications parameter value quantity per reel 4000 pieces reel diameter 13 inches hub diameter 4 inches tape width 16 mm tape pitch 12 mm table 27. cyw20730 7 7 0.8 mm wfbga, 64-pin tape reel specifications parameter value quantity per reel 2500 pieces reel diameter 13 inches hub diameter 4 inches tape width 16 mm tape pitch 12 mm pin 1: top left corner of package toward sprocket holes
32-pin qfn 0c to 70c 40-pin qfn 0c to 70c 64-pin bga 0c to 70c 32-pin qfn 0c to 70c 40-pin qfn 0c to 70c 64-pin bga 0c to 70c document number: 002-14824 rev. *j page 45 of 50 cyw20730 5. ordering information table 28. ordering information part number package ambient operating temperature cyw20730a2kml2g cyw20730a2kmlg cyw20730a2kfbg cyw20730a1kml2g cyw20730a1kmlg cyw20730a1kfbg
document number: 002-14824 rev. *j page 46 of 50 cyw20730 a. appendix: acronyms and abbreviations the following list of acronyms and abbrev iations may appear in this document. term description adc analog-to-digital converter afh adaptive frequency hopping ahb advanced high-performance bus apb advanced peripheral bus apu audio processing unit arm7tdmi-s? acorn risc machine 7 thumb instruction, debugger, multiplier, ice, synthesizable bsc broadcom serial control btc bluetooth controller coex coexistence dfu device firmware update dma direct memory access ebi external bus interface hci host control interface hv high voltage idc initial digital calibration if intermediate frequency irq interrupt request jtag joint test action group lcu link control unit ldo low drop-out lhl lean high land lpo low power oscillator lv logicvision? mia multiple interface agent pcm pulse code modulation pll phase locked loop pmu power management unit por power-on reset pwm pulse width modulation qd quadrature decoder ram random access memory rf radio frequency rom read-only memory rx/tx receive, transmit spi serial peripheral interface sw software uart universal asynchronous receiver/transmitter upi -processor interface
document number: 002-14824 rev. *j page 47 of 50 cyw20730 a.1 references the references in this section may be used in conjunction with this document. note: cypress provides customer access to te chnical documentation and software through its customer support portal (csp) and downloads & support site (see iot resources on page 3 ). for documents, replace the ?x? in the document number with the la rgest number available in the repository to ensure that you ha ve the most current vers ion of the document. wd watchdog document name broadcom number cypress number items [1] single-chip bluetooth? transceiver and baseband processor 20702-ds10x-r 002-14772 term description
document number: 002-14824 rev. *j page 48 of 50 cyw20730 document history document title: cyw20730 single-chip bluetooth transceiver for wireless input devices document number: 002-14824 revision ecn orig. of change submission date description of change ** ? ? 04/27/2010 20730-ds100-ri: initial release *a ? ? 06/25/2010 20730-ds101-r: added: ? ?shutter control for 3d glasses? on page 10. ? ?infrared modulator? on page 10. ? ?infrared learning? on page 11. ? ?triac control? on page 12. ? ?broadcom proprietary control signalling and triggered baseband fast connect? on page 12. ? figure 5: ?internal reset timing,? on page 17. ? figure 6: ?external reset timing,? on page 17. ? figure 10: ?40-pin qfn ball map,? on page 33. ? figure 11: ?64-pin bga ball map,? on page 34. ? ?spi timing? on page 41. ? figure 16: ?40-pin qfn,? on page 44. ? figure 17: ?64-pin fbga,? on page 45. ? revised: ? ?microprocessor unit? on page 16. ? table 6: ?pin descriptions,? on page 25. ? table 11: ?adc specifications,? on page 36. ? table 14: ?receiver rf specifications,? on page 38. ? table 15: ?transmitter rf specifications,? on page 39. ? table 21: ?ordering information,? on page 50. *b ? ? 03/23/2011 20730-ds102-r: added: ? table 1: ?adc modes,? on page 18 revised: ? figure 1: ?functional block diagram,? on page 2 ? ?adc port? on page 17 ? ?internal ldo regulator? on page 22 ? ?uart interface? on page 23 ? table 6: ?xtal oscillator characteristics,? on page 25 ? table 8: ?gpio pin descriptions,? on page 30 ? table 10: ?power supply,? on page 39 ? table 11: ?ldo regulator electr ical specifications,? on page 40 ? table 12: ?adc specifications,? on page 41 ? table 14: ?current consumption,? on page 42 ? table 15: ?receiver rf specifications,? on page 43 ? table 16: ?transmitter rf specifications,? on page 44 ? table 18: ?spi interface timing specifications,? on page 46 ? table 21: ?BCM20730 6 6 1 mm qfn, 40-pin tape reel specifications,? on page 52 ? table 22: ?BCM20730 7 7 .8 mm wfbga, 64-pin tape reel specifications,? on page 52 deleted: ? placeholder for figure 4: triac control ? placeholder for figure 18: BCM20730, 6 x 6 qfn package tray ? placeholder for figure 19: BCM20730, 7 x 7 fbga package tray *c ? ? 04/06/2011 20730-ds103-r: revised: ? table 14: ?current consumption,? on page 42 ? table 23: ?ordering information,? on page 54 *d ? ? 05/09/2011 20730-ds104-r: revised: ? figure 1: ?functional block diagram,? on page 2 ? ?adc port? on page 17 ? table 10: ?power supply,? on page 39
document number: 002-14824 rev. *j page 49 of 50 cyw20730 revision ecn orig. of change submission date description of change *e ? ? 06/29/2011 20730-ds105-r: added: ? figure 9: ?32-pin qfn ball map,? on page 39 ? figure 16: ?32-pin qfn package,? on page 52 ? table 20: ?BCM20730 5 5 1 mm qfn, 32-pin tape reel specifications,? on page 55 revised: ? general description and features on cover ? figure 1: ?functional block diagram,? on page 2 ? ?adc port? on page 17 ? table 2: ?BCM20730 first spi set (master mode),? on page 18 ? table 2: ?BCM20730 first spi set (master mode),? on page 18 ? table 2: ?BCM20730 first spi set (master mode),? on page 18 ? figure 5: ?external reset timing,? on page 22 ? ?gpio port? on page 27 ? ?bbc power management? on page 29 ? table 7: ?pin descriptions,? on page 30 ? table 8: ?gpio pin descriptions,? on page 32 ? table 12: ?adc specifications,? on page 44 *f ? ? 09/20/2011 20730-ds106-r: changed from a preliminary data sheet to a data sheet. *g ? ? 10/10/2012 20730-ds107-r: revised: ? ?spi timing? on page 49 *h ? ? 09/09/2013 20730-ds108-r: revised: ? section 1.3: ?shutter control for 3d glasses,? on page 6 ? table 28, ?ordering information,? on page 45 added: ? table 16, ?esd tolerance,? on page 33 *i 5522944 utsv 11/16/2016 updated to cypress template *j 5700376 aesatmp7 04/25/2017 updated cypress logo and copyright. document title: cyw20730 single-chip bluetooth transceiver for wireless input devices document number: 002-14824
document number: 002-14824 rev. *j revised april 25, 2017 page 50 of 50 cyw20730 ? cypress semiconductor corporation, 2010-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information pr ovided in this document, includ ing any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 cypress developer community forums | wiced iot forums | projects | video | blogs | ?

▲Up To Search▲

Price & Availability of BCM20730

	To Download BCM20730 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .